Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods and structures, including unidirectional metal layout for memory cell, for using improved cell routability for metal lines for manufacturing integrated circuits.
Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative finFET device, which is a 3-dimensional structure. More specifically, in a finFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a trigate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the finFET device only has a dual-gate structure.
FinFET designs use “fins” that may be formed on the surface of a semiconductor wafer using selective-etching processes. The fins may be used to form a raised channel between the gate and the source and drain of a transistor. The gate is then deposited such that it wraps around the fin to form a trigate structure. Since the channel is extremely thin, the gate would generally have a greater control over the carriers within. However, when the transistor is switched on, the shape of the channel may limit the current flow. Therefore, multiple fins may be used in parallel to provide greater current flow for increased drive strength.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art finFET device. A finFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The semiconductor device may be position to a vertical orientation, creating one or more fins 110. The source and drain of the finFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length of the finFET device. The current flow occurs along an orthogonal crystal plane in a direction parallel to the plane of the semiconductor wafer. The electrically significant height of the fin (labeled H) is typically determined by the amount of oxide recess in the fin reveal step and hence is constant for all fins 110.
The thickness of the fin (labeled Tfi) determines the short channel behavior of the transistor device and is usually small in comparison with the height H of the fin 110. The pitch (labeled P) of the fins is determined by lithographic constraints and dictates the wafer area to implement the desired device width. A small value of the pitch P and a large value of the height H enable a better packing of the devices per square area resulting in a denser design, or more efficient use of silicon wafer area.
The scaling down of integrated circuits coupled with higher performance requirements for these circuits have prompted an increased interest in finFETs. FinFETs generally have the increased channel widths, which includes channel portions formed on the sidewalls and top portions of the fins. Since drive currents of the finFETs are proportional to the channel widths, finFETs generally display increase drive current capabilities.
Designers often use pre-designed basic cells to form layouts of more complex cells comprising finFET devices. For example, designers often use a unit SRAM cell to design and fabricate a memory device. In a CMOS integrated circuit, PMOS and NMOS transistor pairing are often used to form circuit cells.
The ultimate goal in integrated circuit fabrication is to accurately reproduce the original circuit design on integrated circuit products. Historically, the feature sizes and pitches employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength immersion photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as multiple patterning, e.g., double patterning. Generally speaking, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features than would otherwise be impossible using existing photolithography tools.
The Self-Aligned-Double-Patterning (SADP) process is one such multiple patterning technique. The SADP process may be an attractive solution for manufacturing next-generation devices, particularly metal routing lines on such next-generation devices, due to better overlay control that is possible when using an SADP process. In SADP processes, metal features that are defined by mandrel patterns are referred to as “mandrel metal,” while metal feature that are not defined by mandrel patterns are called “non-mandrel metal.” Further, SADP processes generally have a high tolerance for overlay errors. Therefore, SADP processes have been increasingly adopted for metal formation in higher resolution designs, such as 14 nm and 10 nm designs.
To use double patterning techniques, an overall target pattern must be what is referred to as double-patterning-compliant. In general, this means that an overall target pattern is capable of being decomposed into two separate patterns that each may be printed in a single layer using existing photolithography tools. Layout designers sometime speak of such patterns with reference to “colors,” wherein the first mask will be represented in an EDA tool using a first color and the second mask will be represented in the EDA tool using a second, different color. To the extent a layout is non-double-patterning-complaint, it is sometimes stated to present a “coloring conflict” between the two masks.
In order to accommodate smaller integrated circuit designs, designers have provided more dense, smaller-track functional cells (e.g., 10-track or lower functional cells). For larger track designs, generally, designers desire to have a unidirectional metal-1 (M1) design where M1 is parallel to the gate (PC) structures, while allocating metal-2 (M2) as power rail. However, with smaller-track designs, in order to complete routing, designers are forced to make M1 bi-directional.
When designing a layout of various devices with an integrated circuits (e.g., CMOS logic architecture), designers often select pre-designed functional or standard cells comprising various features (e.g., diffusion regions, transistors, metal lines, vias, etc.) and place them strategically to provide an active area of an integrated circuit. One challenge of designing a layout is accommodating ever-increasing density of cell components and still maintain routability for connecting various components of the cells. This is increasingly a challenge as dimensions of these components get smaller, such as for 10 nm or lower integrated circuit designs.
Designers often formulate memory cell layout and couple them with pre-designed functional or standard cells. In some cases, the use of these functional cells requires that some of the metal features in memory cell layouts to be of certain directions. In order to reduce spacing between structures of different colors and to avoid “same color” conflicts, the memory cells also include triple metal-1 (M1) structures with bi-directional shapes.
Turning now to FIGS. 2A-2C, stylized depictions metal and contact/gate layers of a single patterned prior art memory cell is illustrated. FIGS. 2A-2C show the formation of a memory bit cell 200 layout using single patterned M1 and M2 structures. The memory cell 200 comprises a cell boundary 210. FIG. 2A shows an M2 layer on which a plurality of M2 structures are formed. A 1st M2 ground structure 201a and a 2nd M2 ground structure 201b are formed coupling a memory cell 200 to a ground signal. A Vdd M2 structure 202 is formed for coupled the cell 200 to a Vdd signal. Further, a power line M2 structure 205 is formed. A positive bit line 204 and a negative bit line 206 are formed using M2 structures.
FIG. 2B shows M1 structures that are formed for creating the memory cell 200. A plurality of horizontal M1 structures 215 are formed. Further, a plurality of contacts 217 are formed for coupling various M1 structures 215 to structures of other layers, e.g., M2 structures.
FIG. 2C shows the formations of contact formation, gate formations, and active layers. The memory cell 200 may comprise a 1st active region 221a, a 2nd active region 221b, a 3rd active region 221c, and a 4th active region 221d (collectively “221”). A plurality of gate formations 223, formed from poly-silicon materials may be formed on the active regions 221, and/or may span one or more active regions 221. A plurality of local contacts 217 (e.g., TS, CA, CB contacts) may be formed for coupling various structures of the cell 200.
One problem associated with the memory bit cell layout of FIGS. 2A-2C is that patterned metal layer structures are formed in larger node cells, such as 28 nm node cells. For these types of cells, the M2 metal structures are formed in a bi-directional configuration. However, bi-directional shapes cannot be used as bit line patterns in 10 nm or smaller node cells for configuring SADP patterning. Generally, SADP patterning requires unidirectional shapes.
Designers have attempted to address some of these problems by using triple patterned metal layer structures. FIGS. 3A-3D stylized depictions metal and contact/gate layers of a triple-patterned, prior art memory cell.
FIG. 3A illustrates a cell boundary 310 of a memory cell 300. A plurality of M2 metal structures 302 are formed on an M2 metal layer. Further, a plurality of vias 303 may be formed for connecting various M2 structures to metal structures in other layers. The M2 structures are formed in a unidirectional, horizontal configuration. In some cases, the minimum spacing between the M2 metal structures 302 can be difficult to maintain in smaller, 14 nm or 10 nm node devices.
FIG. 3B shows an M1 layer of the memory cell 300. A plurality of M1 structures that are generally in a horizontal configuration, are formed. A plurality of M1 structures 313 may be formed at the top portion of the cell border 310. One or more of the M1 structures 313 may be configured for providing VDD connections. One or more vias 315 that may be used to couple the M1 structures 312 to other metal layers.
A plurality of M1 structures 314 may be formed at the bottom portion of the cell border 310. One or more of the M1 structures 314 may be configured for providing VSS connections. One or more vias 316 that may be used to couple the M1 structures 314 to other metal layers.
FIG. 3B also shows that a plurality of M1 structures 313 may be formed in the active regions of the memory cell 300. One or more of the M1 structures 313 may be configured for providing portions of a circuit in active regions of the memory cell 300. One or more vias 317 that may be used to couple the M1 structures 313 of the active regions to other metal layers.
FIG. 3C shows the formations of contact formations and gate formations. A plurality of gate formations 321 may be formed in the cell 300. A plurality of gate cuts 322 provide for forming the gate formations 321. A plurality of M2 structures 323 is shown in FIG. 3C. The gate formations 321 may be electrically coupled to M2 structures 323 using local interconnect structures, such as CA/CB structures 325.
FIG. 3D shows active regions of the memory cell 300. A 1st active region 242a, a 2nd active region 342b, and a 3rd active region 342c may be formed in the cell 300. FIG. 3D also shows a plurality of gate formations 321. Further, a plurality of source/drain fins 345 are also shown in FIG. 3D.
As described above, the triple-patterned memory cell 300 utilizes unidirectional M2 layer structures. One problem associated with this memory cell 300 design is that the standard cell layouts that comprise M2 metal structures with perpendicular shaped poly gate layer structures are not compatible with the unidirectional M2 structures of the memory cell 300. Generally, in 10 nm and smaller node standard cells, the M2 layers with perpendicular shapes (as compared to FIG. 2A), are incompatible with the memory cell design of FIGS. 3A-3D. Therefore, the prior art memory cell designs described in FIGS. 2 and 3 may not be compatible with standard cells of 10 nm or smaller nodes. This creates various problems when designing circuits with memory cells and standard functional cells. Accordingly, as described above, there are various inefficiencies, errors, and other problems associated with the state-of-art.
The present disclosure may address and/or at least reduce one or more of the problems identified above.